1. Field of the Invention
The present invention relates to a bit phase synchronizing method and a bit phase synchronizing circuit suitable for implementing the method.
2. Description of the Related Art
A system composed of plural units such as a broad-band ISDN (Integrated Services Digital Network) switching system distributes a clock signal of the same frequency to each of the units through lines from a common reference clock source. Each unit sends and receives data to and from another unit synchronously with the clock. In case of handling a great amount of data at a very high speed, however, a phase difference between the clock signals received by the units, which is caused by differences in length between the lines for the clock signal, becomes a problem. Therefore, a method is carried out in which each unit synchronizes input data in phase with its own clock signal by being provided with a bit phase synchronizing circuit for adjusting the phase of the input data.
As prior art for this purpose, for example, there is a technique disclosed in Japanese laid-open publication Tokkaihei No.4-293332. This is roughly described in the following. Input data is inputted into a first delay gate group composed of plural delay gates connected in series with one another. Said input data or output data of either delay gate is outputted as output data from the first delay gate group. The output data is inputted into a second delay gate group of two-stage delay gates. Next, it is judged at the same time controlled by a reference clock signal whether or not said inputted data and the output data of the first-stage delay gate of the second delay gate group coincide in logic level with each other, and whether or not the output data of the first-stage delay gate and the output data of the second-stage delay gate coincide in logic level with each other. According to this judgement, a bit change detecting signal is generated which shows whether or not a point of time when the output data from said first-stage delay gate changes in logic level, namely, a bit change point is within a specified time range before and after said judgement time. And in case that the input data and the reference clock signal are not synchronous with each other, in response to the bit change detecting signal, the system performs an automatic phase adjustment so as to synchronize in phase said input data with said reference clock signal by selecting another output data out of plural output data being outputted by said first delay gate group (called selected data) and sending said newly selected output data to the second delay gate group.
In the above-mentioned prior art, stability of the delay time, namely, a delay quantity or duration in each delay gate of the first delay gate group, is significant. Because if the delay quantity in each delay gate of the first delay gate group varies with the lapse of time, each delay gate of the first delay gate group cannot give a phase difference to input data an accurate and repeatable manner. The reason is that since the delay quantity in each delay gate is the minimum unit of phase difference to be adjusted, the phase adjustment resolution comes to be varied. When the phase adjustment resolution is varied, an aimed-at phase adjustment cannot be performed even if an attempt is made to adjust the phase of the input data by changing an output position in the first delay gate group according to the bit change detecting signal.
In said laid-open publication, however, there is no description about stabilization of the delay quantity in the first delay gate group. Even in case each delay gate of the first delay gate group is composed of a CMOS inverter designed so as to have a specified fixed delay quantity for the time, the delay quantity of a signal in the CMOS inverter can deviate greatly from its design value due to the chip temperature or the finished characteristics of the MOS FETs composing the chip.
In order to make a bit phase adjusting circuit with good repeatability of the phase difference, it is necessary to stabilize at least delay quantities in the first delay gate group with the lapse of time. Up to now, however, there has been no conception of suppressing such undesirable variation in the delay gates.
Accordingly, it is an object of the present invention to provide a method for attaining bit phase synchronization, and a circuit suitable for carrying out the method.